library verilog;
use verilog.vl_types.all;
entity ALU_Control is
    port(
        funct           : in     vl_logic_vector(5 downto 0);
        ALUop           : in     vl_logic_vector(2 downto 0);
        ALUctrl         : out    vl_logic_vector(2 downto 0)
    );
end ALU_Control;
